

Article 377 of comp.theory.cell-automata:
Path: mimsy!haven!purdue!decwrl!shelby!portia!portia.stanford.edu!bugboy
>From: [email-masked] (Michael Frank)
Newsgroups: comp.theory.cell-automata
Subject: Wireworld memory units
Message-ID: <[email-masked]>
Date: 8 Mar 90 12:16:03 GMT
Sender: USENET News System <[email-masked]>
Reply-To: [email-masked] (Michael Frank)
Organization: Stanford University
Lines: 86

Hi, I just started reading this group and noticed the wireworld discussion,
and I wondered whether anyone had seen before a design that I came up with
for a memory gate.  Here it is:

...=.....
...=.....
..===....
...=.....
..=.=....
..=.=....
====.====
..=......
.........

The wire on the left is the SET input, the wire on top the CLEAR input, and
the wire on the right is the output.  The inputs and outputs are supposed
to be pulsed at 6-cycle intervals.  Here's a run-through:

Initially there are no electrons in the loop.  At a tick which we'll number
0, an electron enters the device as shown:

...=.....
...=.....
..===....
...=.....
..=.=....
..=.=....
-#==.====
..=......
.........

6 cycles later, it leaves the output, and a duplicate rounds the bottom of
the loop for another cycle, so that the memory will continue outputing
the pulse:

...=.....
...=.....
..===....
...=.....
..=.=....
..=.-....
===#.#===
..=......
.........

But, if at this time (or any multiple of 6 cycles afterwards) a pulse
arrives in the CLEAR input,

...#.....
...=.....
..===....
...=.....
..=.=....
..=.-....
===#.#===
..=......
.........

Then two cycles later, the gate will look like this:

...=.....
...-.....
..###....
...=.....
..#.=....
..-.=....
==-=.=-#=
..-......
.........

And the pulse in the loop will go away, and pulses will stop
coming out the output.

What do you guys think?  Anyone seen a memory unit this small before?

Note the use of the tiny OR gate within it, and the NOT gate at top.
OR gate:
.=.
===
.=.
...
Anyway, hope I didn't use too much bandwidth.
Bye!
Mike Frank
[email-masked]
[email-masked]